1. Field of the Invention
The present invention relates to a resistance compensation method, a circuit having a resistance compensation function, and a circuit resistance test method.
2. Description of the Related Art
In an LSI circuit required in design to perform high-speed data transfer, such as a so-called DDR2 (Double Data Rate 2) memory interface, the termination resistance of the interface part with a memory circuit is adjusted and controlled. In the case of the DDR2 memory interface, the inclusion of a so-called ODT (On Die Termination) function is specified in order to adjust the termination resistance of the interface part between the memory circuit and the LSI circuit. Therefore, for instance, in the ODT circuit of the DDR2 memory interface, it is necessary to include a mechanism for adjusting the termination resistance to 75 Ω or 150 Ω in the LSI circuit.
FIG. 1 shows a diagram (a concept diagram) of a conventional analog termination resistor (ODT) circuit 1 and a termination resistor control circuit 6. FIG. 2 shows the details of the termination resistor control circuit 6.
In this example, the value of a termination resistor 3 is determined by the control circuit 6 connected to a fixed resistor (a reference resistor) 5 serving as a reference. As shown in FIG. 1, the configuration according to this method includes the termination resistor 3 composed of transistors, an input/output buffer 2, and the control circuit 6 for controlling the termination resistance.
The termination resistor control circuit 6 is configured as shown in FIG. 2. In a reference level generation part 6-1 of the control circuit 6, an operational amplifier receives a level in the current path of the series circuit of the reference resistor 5 and a transistor Tr.1, and generates the gate level of a transistor Tr.2. Further, the control circuit 6 includes a transistor Tr.3 connected in series to the transistor Tr.2. The transistor Tr.3 is provided to obtain the same resistance as the reference resistor 5.
Each of transistors Tr.4 and Tr.5 has a function as a switch. The transistors Tr.4 and Tr.5 are controlled by an ODTEN signal, and output respective level signals BIASP and BIASN that control the termination resistance. The level signals BIASP and BIASN are provided from the control circuit 6 to the gates of the corresponding transistors forming the termination resistor 3. The resistance of each of the transistors forming the termination resistor 3 is adjusted so as to be equal to the resistance of the reference resistor 5 by adjusting the gate level.
That is, the transistors (p-channel type and n-channel type FETs) forming the termination resistor 3, and semiconductor devices in the control circuit 6, such as the transistors Tr.1, Tr.2, Tr.3, etc., are all included in the same LSI circuit 1, and are manufactured in the same manufacturing process in the same chip. Accordingly, their characteristics may be substantially the same. Therefore, by realizing the same resistance as that of the reference resistor 5 by each of the transistors Tr.2 and Tr.3 in the control circuit 6, and by extracting the gate levels at that time directly as the level signals BIASP and BIASN and applying them to the gates of the transistors forming the termination resistor 3, the same resistance as the reference resistor 5 can be realized by each of the transistors forming the termination resistor 3.
See Japanese Laid-Open Patent Applications No. 2002-199030 and No. 10-133792.
However, according to the configuration shown in FIGS. 1 and 2, the signal levels of the level signals BIASP and BIASN are analog levels. That is, the resistances of the transistors forming the termination resistor 3 are controlled by controlling the physical state of the transistors with these levels. Accordingly, when interconnection lines for transmitting the level signals BIASP and BIASN are provided inside the LSI, the signals are sensitive to noise generated inside the chip. As a result, it is considered that when voltage applied to the gate terminal of each of the transistors forming the termination resistor 3 is slightly deviated, it is difficult to realize a desired resistance.
In particular, the number of lines forming the interface between an LSI circuit and a memory circuit is generally large. Accordingly, if the control circuit 6 is provided common to the multiple lines, the level signals BIASP and BIASN are provided to each of the corresponding multiple termination resistors 3. As a result, the signals are sensitive to noise.
In order to solve this problem, the control circuit 6 may be provided for each termination resistor 3, for instance. This makes it possible to increase noise immunity. However, this also causes a great increase in the number of terminals of the reference resistor 5 and in chip size, so that a desired specification of circuit size may not be satisfied.